Last shared 41 days ago
VLSI DFT: •Hands on knowledge of EDT Insertion. Scan stitching, MBIST Insertion and IEEE 1149.1/6 insertion. •Hands on knowledge of ATPG, Vector Generation for MBIST, 1149.1/1149.6 Standard. •ATPG Vector Verification, MBIST Verification, 1149.1/1149.6 verification. •Analog BIST, IOBIST, PLL vector Generation and verification. •Good experience in Hierarchical DFT methodology. •Good kno, Logic design. •Coding Experience in Verilog / VHDL/System Verilog HDL languages. •Experienced in De, Synthesis, LEC. •RTL Code Integration. (Both Module level & FullChip Level). •Experience in Cross domain clock, Multi-clock design. VLSI Design Verification: •Hands on knowledge of System Verilog/Verilog/VHDL. , OVM, eRM. •Strong hands-on experience on IP verification, SOC projects. •Good experience in Full chip SOC and unit level validation. •Good knowledge of digit
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